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1. general description the 74lvc16374a and 74lvch16374a are 16-bit edge-triggered flip-flops featuring separate d-type inputs with bus hold (74lvch16374a only) for each flip-flop and 3-state outputs for bus-oriented applications. it consists of two sections of eight positive edge-triggered flip-flops. a clock input (ncp) and an output enable (noe ) are provided for each octal. the flip-flops store the state of their individual d-inputs that meet the set-up and hold time requirements on the low-to-high clock (cp) transition. when pin noe is low, the contents of the flip-flops are available at the outputs. when pin noe is high, the outputs go to the high-impedance off-state. operation of input noe does not affect the state of the flip-flops. inputs can be driven from either 3.3 v or 5 v devices. when disabled, up to 5.5 v can be applied to the outputs. these features allow the use of these device s in mixed 3.3 v and 5 v applications. bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. features and benefits ? 5 v tolerant inputs/outputs for interfacing with 5 v logic ? wide supply voltage range from 1.2 v to 3.6 v ? cmos low power consumption ? multibyte flow-through standard pinout architecture ? low inductance multiple supply pins for minimum noise and ground bounce ? direct interface with ttl levels ? all data inputs have bus hold (74lvch16374a only) ? high-impedance outputs when v cc = 0 v ? complies with jedec standard: ? jesd8-7a (1.65 v to 1.95 v) ? jesd8-5a (2.3 v to 2.7 v) ? jesd8-c/jesd36 (2.7 v to 3.6 v) ? esd protection: ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-b exceeds 200 v ? cdm jesd22-c101e exceeds 1000 v ? specified from ? 40 ? c to +85 ? c and ? 40 ? c to +125 ? c 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type f lip-flop; 5 v tolerant; 3-state rev. 11 ? 16 january 2013 product data sheet
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 2 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74lvc16374adl ? 40 ? cto+125 ? c ssop48 plastic shrink small outline package; 48 leads; body width 7.5 mm sot370-1 74lvch16374adl 74lvc16374adgg ? 40 ? cto+125 ? c tssop48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 74lvch16374adgg 74lvc16374abx ? 40 ? cto+125 ? c hxqfn60u plastic thermal enhanc ed extremely thin quad flat package; no leads; 60 terminals; utlp based; body 4 ? 6 ? 0.5 mm sot1134-1 74LVCH16374ABX pin numbers are shown for ssop48 and tssop48 packages only. pin numbers are shown for ssop48 and tssop48 packages only. fig 1. logic symbol fig 2. iec logic symbol 001aaa253 1q0 1q1 1cp 2cp 1q2 1q3 1q4 1q5 1q6 1q7 1oe 47 46 48 25 44 43 41 40 38 37 2 3 1 5 6 8 9 11 12 24 2q0 2q1 2q2 2q3 2q4 2q5 2q6 2q7 1d0 1d1 1d2 1d3 1d4 1d5 1d6 1d7 2d0 2d1 2d2 2d3 2d4 2d5 2d6 2d7 36 35 33 32 30 29 27 26 13 14 16 17 19 20 22 23 2oe 23 001aaa254 37 12 11 9 8 6 5 47 46 44 43 41 40 38 1d7 1d0 1d1 1d2 1d3 1d4 1d5 1d6 2 3 1q7 1q6 1q5 1q4 1q3 1q2 1q0 1q1 26 22 20 19 17 16 36 35 33 32 30 29 27 2d5 2d0 2d1 2d2 2d3 2d4 13 14 2q5 2q4 2q3 2q2 2q1 2q0 24 25 en2 1oe 1 en1 1cp 2oe 2cp 48 c3 c4 3d 1 4d 2d7 2d6 2q7 2q6 2
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 3 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state fig 3. logic diagram 001aaa255 1cp 1oe to 7 other channels d cp q ff1 1q0 1d0 2cp 2oe to 7 other channels d cp q ff2 2q0 2d0 fig 4. bus hold circuit to internal circuit mna705 v cc data input
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 4 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state 5. pinning information 5.1 pinning fig 5. pin configuration sot370-1 (ssop48) and sot362-1 (tssop48) 74lvc16374a 74lvch16374a 001aaa231 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1q0 1q1 gnd 1d0 1d1 gnd 1oe 1cp 1q2 1q3 v cc 1q4 1q5 gnd 1q6 1q7 2q0 2q1 gnd 2q2 2q3 v cc 2q4 2q5 gnd 2q6 2q7 2oe 1d2 1d3 v cc 1d4 1d5 gnd 1d6 1d7 2d0 2d1 gnd 2d2 2d3 v cc 2d4 2d5 gnd 2d6 2d7 2cp
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 5 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state (1) the die substrate is attached to this p ad using conductive die attach material. it cannot be used as a supply pin or input. fig 6. pin configuration sot1134-1 (hxqfn60u) d1 d3 a16 a15 a14 a13 a12 a11 d2 b9 gnd (1) b10 d7 a17 a18 b11 a19 b12 a20 b13 a21 b14 b8 a10 d6 a9 a8 b7 b6 a7 b5 a6 a22 b15 a23 b16 a24 b17 a25 a26 d8 d4 a27 b18 a28 a29 b19 b20 a30 a31 a32 b4 a5 b3 b2 b1 d5 a4 a3 a2 a1 74lvc16374a 74lvch16374a 001aaj618 transparent top view terminal 1 index area
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 6 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state 5.2 pin description 6. functional description [1] h = high voltage level; h = high voltage level one set-up time prior to the high-to-low cp transition; l = low voltage level; l = low voltage level one set-up time prior to the high-to-low cp transition; ? = low-to-high transition; z = high-impedance off-state. 7. limiting values table 2. pin description symbol pin description sot370-1 and sot362-1 sot1134-1 1oe , 2oe 1, 24 a30, a13 output enab le input (active low) gnd 4, 10, 15, 21, 28, 34, 39, 45 a32, a3, a8 , a11, a16, a19, a24, a27 ground (0 v) v cc 7, 18, 31, 42 a1, a10, a17, a26 supply voltage 1q0 to 1q7 2, 3, 5, 6, 8, 9, 11, 12 b20, a31, d5, d1, a2, b2, b3, a5 data output 2q0 to 2q7 13, 14, 16, 17, 19, 20, 22, 23 a6, b5, b6, a9, d2, d6, a12, b8 data output 1d0 to 1d7 47, 46, 44, 43, 41, 40, 38, 37 b18, a28, d8, d4, a25, b16, b15, a22 data input 2d0 to 2d7 36, 35, 33, 32, 30, 29, 27, 26 a21, b13, b12, a18, d3, d7, a15, b10 data input 1cp, 2cp 48, 25 a29, a14 clock input table 3. function selection [1] operating mode input internal flip-flop output nq0 to nq7 noe ncp ndn load and read register l ? ll l l ? hh h load register and disable outputs h ? ll z h ? hh z table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +6.5 v i ik input clamping current v i <0v ? 50 - ma v i input voltage [1] ? 0.5 +6.5 v i ok output clamping current v o >v cc or v o <0v - ? 50 ma v o output voltage outpu t high-or low-state [2] ? 0.5 v cc +0.5 v output 3-state [2] ? 0.5 +6.5 v i o output current v o =0 vtov cc - ? 50 ma i cc supply current - 100 ma i gnd ground current ? 100 - ma t stg storage temperature ? 65 +150 ?c
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 7 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state [1] the minimum input voltage ratings may be excee ded if the input current ratings are observed. [2] the output voltage ratings may be exceeded if the output current ratings are observed. [3] above 60 ? c, the value of p tot derates linearly with 5.5 mw/k. [4] above 70 ? c, the value of p tot derates linearly with 1.8 mw/k. 8. recommended operating conditions 9. static characteristics p tot total power dissipation t amb = ? 40 ? c to +125 ?c (t)ssop48 package [3] -5 0 0m w hxqfn60u package [4] -1 0 0 0m w table 4. limiting values ?continued in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit table 5. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 1.65 - 3.6 v functional 1.2 - - v v i input voltage 0 - 5.5 v v o output voltage active mode 0 - v cc v power-down mode; v cc =0v 0 - 5.5 v t amb ambient temperature ? 40 - +125 ?c ? t/ ? v input transition rise and fall rate v cc = 1.65 v to 2.7 v 0 - 20 ns/v v cc = 2.7 v to 3.6 v 0 - 10 ns/v table 6. static characteristics at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max v ih high-level input voltage v cc = 1.2 v 1.08 - - 1.08 - v v cc = 1.65 v to 1.95 v 0.65 ? v cc - - 0.65 ? v cc -v v cc = 2.3 v to 2.7 v 1.7 - - 1.7 - v v cc = 2.7 v to 3.6 v 2.0 - - 2.0 - v v il low-level input voltage v cc = 1.2 v - - 0.12 - 0.12 v v cc = 1.65 v to 1.95 v - - 0.35 ? v cc -0.35 ? v cc v v cc = 2.3 v to 2.7 v - - 0.7 - 0.7 v v cc = 2.7 v to 3.6 v - - 0.8 - 0.8 v
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 8 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state v oh high-level output voltage v i =v ih or v il i o = ? 100 ? a; v cc =1.65vto3.6v v cc ? 0.2 v cc -v cc ? 0.3 - v i o = ? 4ma; v cc = 1.65 v 1.2 - - 1.05 - v i o = ? 8ma; v cc = 2.3 v 1.8 - - 1.65 - v i o = ? 12 ma; v cc = 2.7 v 2.2 - - 2.05 - v i o = ? 18 ma; v cc = 3.0 v 2.4 - - 2.25 - v i o = ? 24 ma; v cc = 3.0 v 2.2 - - 2.0 - v v ol low-level output voltage v i =v ih or v il i o = 100 ? a; v cc = 1.65 v to 3.6 v - 0 0.2 - 0.3 v i o =4ma; v cc = 1.65 v - - 0.45 - 0.65 v i o =8ma; v cc = 2.3 v - - 0.6 - 0.8 v i o =12ma; v cc = 2.7 v - - 0.4 - 0.6 v i o =24ma; v cc = 3.0 v - - 0.55 - 0.8 v i i input leakage current v cc = 3.6 v; v i = 5.5 v or gnd [2] - ? 0.1 ? 5- ? 20 ? a i oz off-state output current v i =v ih or v il ; v cc = 3.6 v; v o =5.5vorgnd [2] - ? 0.1 ? 5- ? 20 ? a i off power-off leakage current v cc = 0 v; v i or v o = 5.5 v - ? 0.1 ? 10 - ? 20 ? a i cc supply current v cc = 3.6 v; v i =v cc or gnd; i o =0a -0.120 - 80 ? a ? i cc additional supply current per input pin; v cc = 2.7 v to 3.6 v; v i =v cc ? 0.6 v; i o =0a - 5 500 - 5000 ? a c i input capacitance v cc = 0 v to 3.6 v; v i =gndtov cc -5.0- - -pf i bhl bus hold low current v cc = 1.65; v i = 0.58 v [3] [4] 10 - - 10 - ? a v cc = 2.3; v i = 0.7 v 30 - - 25 - ? a v cc = 3.0; v i = 0.8 v 75 - - 60 - ? a i bhh bus hold high current v cc = 1.65; v i = 1.07 v [3] [4] ? 10 - - ? 10 - ? a v cc = 2.3; v i = 1.7 v ? 30 - - ? 25 - ? a v cc = 3.0; v i = 2.0 v ? 75 - - ? 60 - ? a i bhlo bus hold low overdrive current v cc = 1.95 v [3] [5] 200 - - 200 - ? a v cc = 2.7 v 300 - - 300 - ? a v cc = 3.6 v 500 - - 500 - ? a table 6. static characteristics ?continued at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 9 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state [1] all typical values are measured at v cc = 3.3 v (unless stated otherwise) and t amb =25 ? c. [2] the bus hold circuit is switched off when v i >v cc allowing 5.5 v on the input pin. [3] valid for data inputs (74lvch16374a) only; control inputs do not have a bus hold circuit. [4] the specified sustaining current at the data inputs holds the input below the specified v i level. [5] the specified overdrive current at the data input fo rces the data input to the opposite logic input state. 10. dynamic characteristics i bhho bus hold high overdrive current v cc = 1.95 v [3] [5] ? 200 - - ? 200 - ? a v cc = 2.7 v ? 300 - - ? 300 - ? a v cc = 3.6 v ? 500 - - ? 500 - ? a table 6. static characteristics ?continued at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max table 7. dynamic characteristics voltages are referenced to gnd (ground = 0 v). for test circuit see figure 10 . symbol parameter conditions ? 40 ? c to +85 ? c ? 40 ? c to +125 ?c unit min typ [1] max min max t pd propagation delay ncp to nqn; see figure 7 [2] v cc = 1.2 v - 14 - - - ns v cc = 1.65 v to 1.95 v 2.1 6.9 13.5 2.1 15.6 ns v cc = 2.3 v to 2.7 v 1.5 3.7 6.7 1.5 7.7 ns v cc = 2.7 v 1.5 3.4 6.0 1.5 7.5 ns v cc = 3.0 v to 3.6 v 1.5 3.1 5.4 1.5 7.0 ns t en enable time noe to nqn; see figure 9 [2] v cc = 1.2 v - 20 - - - ns v cc = 1.65 v to 1.95 v 1.5 5.9 13.1 1.5 15.1 ns v cc = 2.3 v to 2.7 v 1.5 3.4 6.9 1.5 8.0 ns v cc = 2.7 v 1.5 3.6 6.0 1.5 7.5 ns v cc = 3.0 v to 3.6 v 1.0 2.7 5.2 1.0 6.5 ns t dis disable time noe to nqn; see figure 7 [2] v cc = 1.2 v - 12 - - - ns v cc = 1.65 v to 1.95 v 2.8 4.6 9.1 2.8 10.5 ns v cc = 2.3 v to 2.7 v 1.0 2.5 4.9 1.0 5.7 ns v cc = 2.7 v 1.5 3.4 5.1 1.5 6.5 ns v cc = 3.0 v to 3.6 v 1.5 3.1 4.9 1.5 6.5 ns t w pulse width ncp high; see figure 7 v cc = 1.65 v to 1.95 v 5.0 - - 5.0 - ns v cc = 2.3 v to 2.7 v 4.0 - - 4.0 - ns v cc = 2.7 v 3.0 - - 3.0 - ns v cc = 3.0 v to 3.6 v 3.0 1.5 - 3.0 - ns
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 10 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state [1] typical values are measured at t amb =25 ? c and v cc = 1.2 v, 1.8 v, 2.5 v, 2.7 v and 3.3 v respectively. [2] t pd is the same as t plh and t phl . t en is the same as t pzl and t pzh . t dis is the same as t plz and t phz . [3] skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. [4] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz c l = output load capacitance in pf v cc = supply voltage in volts n = number of inputs switching ? (c l ? v cc 2 ? f o ) = sum of the outputs t su set-up time ndn to ncp; see figure 8 v cc = 1.65 v to 1.95 v 4.0 - - 4.0 - ns v cc = 2.3 v to 2.7 v 3.0 - - 3.0 - ns v cc = 2.7 v 1.9 - - 1.9 - ns v cc = 3.0 v to 3.6 v 1.9 0.3 - 1.9 - ns t h hold time ndn to ncp; see figure 8 v cc = 1.65 v to 1.95 v 3.0 - - 3.0 - ns v cc = 2.3 v to 2.7 v 2.5 - - 2.5 - ns v cc = 2.7 v 1.1 - - 1.1 - ns v cc = 3.0 v to 3.6 v +1.5 ? 0.3 - 1.5 - ns f max maximum frequency see figure 7 v cc = 1.65 v to 1.95 v 100 - - 80 - ns v cc = 2.3 v to 2.7 v 125 - - 100 - ns v cc = 2.7 v 150 - - 120 - mhz v cc = 3.0 v to 3.6 v 150 300 - 120 - mhz t sk(o) output skew time v cc = 3.0 v to 3.6 v [3] - - 1.0 - 1.5 ns c pd power dissipation capacitance per input; v i =gndtov cc [4] v cc = 1.65 v to 1.95 v - 14.1 - - - pf v cc = 2.3 v to 2.7 v - 16.4 - - - pf v cc = 3.0 v to 3.6 v - 18.5 - - - pf table 7. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v). for test circuit see figure 10 . symbol parameter conditions ? 40 ? c to +85 ? c ? 40 ? c to +125 ?c unit min typ [1] max min max
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 11 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state 11. waveforms measurement points are given in table 8 . v ol and v oh are the typical output voltage levels that occur with the output load. fig 7. clock (ncp) to output (nqn) propagation delays, clock pulse width, and the maximum frequency 001aaa256 ncp input nqn output t phl t plh t w v oh v i gnd v ol v m v m v m 1/f max measurement points are given in table 8 . the shaded areas indicate when the input is permitted to change for predictable performance. v ol and v oh are the typical output voltage levels that occur with the output load. fig 8. data set-up and hold times fo r the ndn input to the ncp input 001aaa257 gnd gnd t h t su t h t su v m v m v m v i v oh v ol v i nqn output ncp input ndn input
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 12 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state measurement points are given in table 8 . v ol and v oh are the typical output voltage levels that occur with the output load. fig 9. 3-state enable and disable times mna362 t plz t phz outputs disabled outputs enabled v y v x outputs enabled output low-to-off off-to-low output high-to-off off-to-high noe input v i v ol v oh v cc v m gnd gnd t pzl t pzh v m v m table 8. measurement points supply voltage input output v cc v i v m v m v x v y 1.2 v v cc 0.5 ? v cc 0.5 ? v cc v ol + 0.15 v v oh ? 0.15 v 1.65 v to 1.95 v v cc 0.5 ? v cc 0.5 ? v cc v ol + 0.15 v v oh ? 0.15 v 2.3 v to 2.7 v v cc 0.5 ? v cc 0.5 ? v cc v ol + 0.15 v v oh ? 0.15 v 2.7 v 2.7 v 1.5 v 1.5 v v ol + 0.3 v v oh ? 0.3 v 3.0 v to 3.6 v 2.7 v 1.5 v 1.5 v v ol + 0.3 v v oh ? 0.3 v
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 13 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state test data is given in table 9 . definitions for test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = external voltage for measuring switching times. fig 10. test circuit for measuring switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aae331 v ext v cc v i v o dut c l r t r l r l g table 9. test data supply voltage input load v ext v i t r , t f c l r l t plh , t phl t plz , t pzl t phz , t pzh 1.2 v v cc ? 2 ns 30 pf 1 k ? open 2 ? v cc gnd 1.65 v to 1.95 v v cc ? 2 ns 30 pf 1 k ? open 2 ? v cc gnd 2.3 v to 2.7 v v cc ? 2 ns 30 pf 500 ? open 2 ? v cc gnd 2.7v 2.7v ? 2.5 ns 50 pf 500 ? open 2 ? v cc gnd 3.0vto3.6v 2.7v ? 2.5 ns 50 pf 500 ? open 2 ? v cc gnd
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 14 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state 12. package outline fig 11. package outline sot370-1 (ssop48) unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 1.4 0.25 10.4 10.1 1.0 0.6 1.2 1.0 0.85 0.40 8 0 o o 0.18 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot370-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 48 25 mo-118 24 1 ssop48: plastic shrink small outline package; 48 leads; body width 7.5 mm sot370-1 a max. 2.8
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 15 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state fig 12. package outline sot362-1 (tssop48) unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.2 0.1 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot362-1 99-12-27 03-02-19 w m tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 a max. 1.2 0 2.5 5 mm scale mo-153
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 16 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state fig 13. package outline sot1134-1 (hxqfn60u) references outline version european projection issue date iec jedec jeita sot1134-1 - - - - - - - - - sot1134-1_po 08-12-17 09-01-22 unit mm max nom min 0.50 0.48 0.46 0.05 0.02 0.00 4.1 4.0 3.9 1.90 1.85 1.80 6.1 6.0 5.9 3.90 3.85 3.80 1 2.5 4.5 0.125 0.075 0.025 0.07 a dimensions hxqfn60u: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; utlp based; body 4 x 6 x 0.5 mm sot1134-1 a 1 b 0.35 0.30 0.25 dd h ee h 0.08 0.1 yy 1 e 0.5 e 1 e 2 e 3 3 e 4 er 0.5 k 0.25 0.20 0.15 l 0.35 0.30 0.25 l 1 v 0.05 w 0 2.5 5 mm scale ac b v c w b a terminal 1 index area d e c y c y 1 x detail x a a 1 e r e 3 e 4 e 2 e 1 e e 1/2 e 1/2 e b ac b v c w k l b20 b18 a27 d8 d4 a32 d5 d7 d6 d1 d3 d2 d h e h l 1 terminal 1 index area a11 a16 b10 b8 a17 b11 b17 a26 a1 b1 a10 b7
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 17 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state 13. abbreviations 14. revision history table 10. abbreviations acronym description cdm charged device model dut device under test esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes 74lvc_lvch16374a v.11 20130116 product data sheet - 74lvc_lvch16374a v.10 modifications: ? minor non-technical text changes and corrections ? document revision history correction 74lvc_lvch16374a v.10 20120301 product data sheet - 74lvc_lvch16374a v.9 74lvc_lvch16374a v.9 20111219 product data sheet - 74lvc_lvch16374a v.8 74lvc_lvch16374a v.8 20110621 product data sheet - 74lvc_lvch16374a v.7 74lvc_lvch16374a v.7 20100323 product data sheet - 74lvc_lvch16374a v.6 74lvc_lvch16374a v.6 20090212 product data sheet - 74lvc_lvch16374a v.5 74lvc_lvch16374a v.5 20031212 product specification - 74lvc_h16374a v.4 74lvc_h16374a v.4 19980317 product specification - 74lvc16374a_ 74lvch16374a v.3 74lvc16374a_ 74lvch16374a v.3 19980317 product specification - 74lvc16374a v.2 74lvc16374a v.2 19970822 product specification - 74lvc16374a v.1 74lvc16374a v.1 - - - -
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 18 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74lvc_lvch16374a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 11 ? 16 january 2013 19 of 20 nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74lvc16374a; 74lvch16374a 16-bit edge-triggered d-type fl ip-flop; 5 v tolerant; 3-state ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 16 january 2013 document identifier: 74lvc_lvch16374a please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 functional description . . . . . . . . . . . . . . . . . . . 6 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 recommended operating conditions. . . . . . . . 7 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 18 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 16 contact information. . . . . . . . . . . . . . . . . . . . . 19 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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